Method and related processing circuits for reducing memory accessing while performing de/compressing of multimedia files

ABSTRACT

Method and apparatus for reducing memory access while de/compressing multimedia files, videos, or image files. An image is divided into blocks, and a frequency data matrix corresponding to a frequency transformed and quantized block is stored in a memory for later de/compression. The method includes registering a bit plane containing a plurality of bits in a register module, wherein each bit represents whether a corresponding element of the data matrix equals zero. While accessing the memory for the data matrix, if a bit of the bit plane shows that its corresponding element of the data array is zero, the element is not accessed from the memory. In checking bits corresponding to elements not yet accessed; if these bits show that elements not accessed are all zero, accessing for the data array can be terminated without accessing them. Thus, memory access can be reduced to occupy less bandwidth of the memory.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention provides a method and related apparatus forreducing memory accessing while de/compressing multimedia files, andmore particularly, a method and related apparatus for reducing memoryaccess by preventing access of null data in the frequency domain.

2. Description of the Prior Art

Since signal detection and processing techniques have been developed andimproved upon, media signals, whether static images or motion videos,can be stored, processed, or transmitted by electronic signals withlittle distortion. However, in general, file sizes of multimedia files,including a variety of media information, are so large that they must becompressed properly for storing and transmitting. Consequently,compressed multimedia files should be decompressed to play. Moreover,because image data of multimedia files are rich in high-dimensional data(including two-dimensional images and/or time-domain changes),de/compression processes place high demand on system resources.Therefore, a key development issue in modern information technology ishow to de/compress image data files with high efficiency and low cost.

Please refer to FIG. 1, which is a schematic diagram illustrating atypical image compression process, such as the process under MPEGprotocol, or Motion Picture Expert Group. Those skilled in the art willrecognize that image compression is seen as a coding process for imagedata, and decompression contrarily a decoding process. As FIG. 1illustrates, a motion image data M (such as a movie or an animation) canbe seen as a series of static pictures, A1, A2, A3, A4, A5, etc.Displayed different pictures as time changes, the motion image data Mcan be a movie. Besides, in order to increase compression rate, aprocess 10 undergoes an inter-coding among pictures initially to analyzeeach difference among pictures as the image data M is compressed; then,a process 12 takes an intra-coding process in a picture based on theoutcome of the process 10.

Those skilled in the art will recognize that the differences amongpictures are little when displaying a series image of running actions.For example, in FIG. 1, a movie formed by the pictures A1, A2, A3displays a motion: an object Oj moves in the same background Bk. Withexception of the object Oj position different in varied pictures, thebackground Bk image does not change a lot. In the process 10, a motiondetection is taken to compare pictures. As FIG. 1 illustrates, themotion detection in the picture A1, A2 can roughly conclude that theobject Oj moves but the background Bk does not change. Furthermore, avector V12 is computed to represent moving direction and distance of theobject Oj. In other words, the picture A2 can roughly be obtained bymoving the object Oj in the picture A1 along with the vector V12, thisprocesses being named dynamic (or action) compensation. A predictivepicture of the picture A2 operated by shifting the object Oj in thepicture A1 along with the vector V12 can be a prediction P2, not shownin FIG. 1. Indeed, the prediction P2 may not absolutely match thepicture A2 (such as reflected light on the object Oj changes a littlebetween the pictures A1 and A2), but their differences should not besignificant. Hence, subtracting the prediction P2 from the picture A2generates a difference picture, named difference D12. That is to say,the picture A2 can be gained by dynamically compensating the picture A1and adding the difference D12, and this means that all image informationof the pictures A1 and A2 can be contained by the picture A1, the vectorV12 and the difference D12. In addition, owing to little imageinformation in the difference D12 and slight differences between theprediction P2 and the picture A2, a high level compression ispracticable, and the pictures A1, A2 are compressed.

Based on the same method, the picture A3 in FIG. 1 can be obtained fromthe picture A2, the corresponding vector V23, and the difference D23, sothat the movie composed of a series of the pictures A1, A2, A3 can beexpressed by the picture A1, the differences D12, D23 and the vectorsV12, V23, thus an initial compression to the series motion image isperformed. Certainly, the data image M may contain so many irrelativesequences, like pictures A4 and A5, that there might be an entirelydifferent object moving in an entirely different background; therefore,the picture A4 is much different from the picture A3, and the motiondetection is cancelled between the pictures A3 and A4, but is executedbetween the pictures A4 and A5 to take compression for the series imageof the pictures A4 and A5 in the process 10.

After compressing/coding the differences among pictures in the process10, the process 12 compresses/codes the pictures or the differencesrespectively. For example, in FIG. 1, the pictures A1, A4 and thedifferences D12, D23, D45 can be further compressed to increasecompression rate. Please refer to FIG. 2, which illustrates acompression (or coding) process of in the process 12. To furthercompress a picture A (like pictures A1, A4, the differences D12, D23,etc.), the picture A is divided into a plurality of small blocks Bformed by a plurality of pixels Bij. The frequency domain data matrix Ccontaining a plurality of data elements Cij is obtained bytwo-dimensional frequency-domain transformations within each block B(such as discrete cosine transformation, or DCT). In other words, eachdata element Cij represents the quantity (i.e. the frequency domaincomponent or coefficient) of the block B in frequency domain. Combiningeach Qij, the quantized data element Cij, can construct the frequencydomain data matrix Q, or frequency domain matrix. Arranging each dataelement Qij of the data matrix Q in a specified order to be a series ofone-dimensional data matrix S is called a serial scanning. Anotherone-dimensional data matrix R is gained after a running length coding tothe data matrix S. Then, a data matrix H is generated after Huffmancoding to the data matrix R. Combining data matrix H corresponding theblock B finishes coding the pictures A.

In the process 12, because each block B is just a part of the picture A,values of pixel Bijs in a block B should not be significant, that is,the values of pixels in the same block tend to be similar. After theblock B undergoes the frequency-domain transformation/quantization, thisrepresents that high frequency domain quantities of the data element Cijand Qij should almost be null, or be negligible. That is to say, thefrequency domain data matrix C and Q are sparse matrices. Therefore,after the one-dimensional matrix S is scanned and arranged from the datamatrix Q, data elements Sks (each equals to one data element Qij) of thedata matrix S are among many null values. As the data matrix S undergoesthe running length coding, numbers of null data elements between twonon-null data elements Sks are coded to reduce the length of the datamatrix S. For example, when ten null data elements exist between twonon-null data elements Si and Sj, it does not store the ten null dataelements between Si and Sj, but records the number of ten null dataelements by the running length coding to the data element Sj. So, thebit length of the data matrix R generated from the running length codingof the data matrix S can be reduced a lot. After Huffman coding, the bitlength of the data matrix R is further compressed, and a data matrix His generated. Combining each data matrix H generated from thecompression of each block B, the compressed picture of the picture Abecomes a multimedia file.

Obviously, if the image data is static, it undergoes the process 12without the process 10, such as a joint Photo-graphic Experts Group, orJPEG, process. Please refer to FIG. 2 (and FIG. 1) again. Thedecompression process is basically the reverse of the compressionprocess. The data matrix H of a compressed multimedia file isdecompressed to the data matrix S, and then is arranged to thetwo-dimensional data matrix Q (named inverse scanning). Dequantizing thedata matrix Q obtains the frequency domain data matrix C. The block Bcan be obtained by taking an inverse discrete cosine transformation tothe data matrix C. Combining varied blocks B obtains the picture A. Ifthe original image data is a motion image data, the original motionimage data can be combined by dynamically compensating the picture A,thereby finishing the decompression (or decoding).

Please refer to FIG. 3 illustrating a function block diagram of a priorart processing circuit 20. The processing circuit 20 performsde/compression (or de/coding) for image data, and includes a centralprocessing unit 14, a memory access module 16, a dynamic estimationmodule 18, a frequency-domain transformation/quantization module 22, aninverse frequency-domain transformation/dequantization module 24, and aninner memory 28 (such as random access memory). The central processingunit 14 controls operations of processing circuit 20. The memory accessmodule 16 can achieve the function of direct memory access, or DMA, sothat the processing circuit 20 can access an outer memory 26 (such asloading the image data waiting for compression from the outer memory26). In the process 10 shown in FIG. 1, the dynamic estimation module 18can take dynamic estimation. In the process 12 in FIG. 1, thefrequency-domain transformation/quantization module 22 can achievefrequency-domain transformation and quantization. Contrarily, theinverse frequency-domain transformation/dequantization module 24 canrecover compressed multimedia files from one-dimensional data matrixesto two-dimensional blocks in order to decompress (decode) and generateeach picture. To support operations of each module in the processingcircuit 20, the processing circuit 20 also includes an inner memory 28to register data for the operations of each module.

For example, when image data compression (coding) is performed by theprior art processing circuit 20, the frequency-domaintransformation/quantization module 22 transforms/quantizes the block Bof each picture (please refer to FIG. 2) to the two-dimensional datamatrix Q, and each data element Qij of the data matrix Q is written(stored) into the inner memory 28 sequentially. Progressing to serialscanning, each data element of the data matrix Q is read from the innermemory 28 sequentially and forms a one-dimensional data matrix S. Then,the next block B is processed.

In summary, it is necessary to access the inner memory 28 frequently inthe prior art processing circuit 20. As FIG. 1 and FIG. 2 show, a dataimage M may include a lot of pictures A, and a picture A contains a lotof blocks B each corresponding to the frequency domain data matrix Q.When the processing circuit 20 compresses images, each data element Qijof the data matrix Q is stored into the inner memory 28 one by one.Besides, when serial scanning, each data element Qij is readsequentially. Actually, as mentioned above, the frequency domain matrixQ might be a sparse matrix, which means that most data elements Qij arenulls, and this is the reason that the running length coding can reducethe length of the matrix S in that the data matrix R only records thenumber of null data elements after running length coding, instead ofarranging these null data element exactly in the data matrix R. However,when the prior art processing circuit 20 accesses the data matrix Q fromthe inner memory 28, there is no better way to utilize characters of asparse matrix, but to access each data element Qij one by one. As aresult, the processing circuit 20 needs to access its inner memory 28frequently in the de/coding process, so that its occupied memoryresources cannot be reduced effectively. In achieving the function ofhigh speed de/compression, the processing circuit 20 should use highfrequency inner memory (that is, it must access more data in a unit oftime), so that the cost of circuit design and manufacture cannot bereduced.

SUMMARY OF INVENTION

It is therefore a primary objective of the claimed invention to providea method and related processing circuits that can de/compress image datawithout frequently accessing memory in order to solve theabove-mentioned problems.

According to the claimed invention, a method includes obtaining a datamatrix made up of a plurality of data elements; and constructing areference matrix based on the data matrix, so that the reference matrixincludes a plurality of reference elements each corresponding to a dataelement, and each reference element represents whether its correspondingdata element fits a default or not. Finally, the method also includestaking a decision step to each data element when the data matrix iswritten into a memory, so that when a reference element corresponding toa data element represents that the data element fits the default, thedata element is prevented from being written into the memory.

These and other objectives of the claimed invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic diagram of typical image data compression.

FIG. 2 illustrates each compression step of each picture in FIG. 1.

FIG. 3 is a function block diagram of a prior art processing circuit ofimage data de/compression.

FIG. 4 is a function block diagram of the present invention.

FIG. 5 depicts a schematic diagram of a bit plane stored in a registermodule in FIG. 4.

FIG. 6 illustrates that the processing circuit in FIG. 4 generates thebit plane according to a frequency domain data matrix.

FIG. 7 is a schematic diagram of the generated bit plane of FIG. 6.

FIG. 8 is a schematic diagram of the quantization correction process ofthe register module in FIG. 4.

FIG. 9 to FIG. 11 are three types of different scanning sequences whenthe processing circuit processes the serial scanning in FIG. 4.

FIG. 12 and FIG. 13 illustrate the refresh process of its correspondingbit plane when the processing circuit in FIG. 4 takes the serialscanning for the frequency domain data matrix in FIG. 6.

FIG. 14 is a implementation diagram of the register module in FIG. 4.

FIGS. 15, 16 illustrate that the register module in FIG. 14 processesshift keying in different conditions.

FIG. 17 is another implementation function block diagram of the presentinvention.

FIG. 18 is a schematic diagram of shift keying by rotation method inFIG. 17.

FIG. 19 is a schematic diagram of an algorithm when the processingcircuit in FIG. 17 processes the one-dimensional inversefrequency-domain transformation.

DETAILED DESCRIPTION

Please refer to FIG. 4, which illustrates a function block diagram ofthe present invention, an implementation of the processing circuit 30.The processing circuit 30 can compress image data (or code the imagedata to a smaller size file), and includes: a central processing unit32, a memory access module 36, a dynamic estimation module 38, a innermemory 52, a frequency-domain transformation/quantization module 40. Inorder to achieve the present invention, the processing circuit 30further includes: a data address generator 46, a decision module 48A, achecking module 48B, a register module 50, and a shift keying controlmodule 54. The central processing unit 32 controls operations of theprocessing circuit 30, and the memory access module 36 directly accessesan outer memory 34. The dynamic estimation module 38 can perform dynamicestimation. The frequency-domain transformation/quantization module 40includes: a frequency-domain transformation module 42A, a quantizationmodule 42B, and a quantization correction module 42C. Thefrequency-domain transformation module 42A transforms a block B (pleaserefer to FIG. 2) to a frequency domain data matrix C by frequency-domaintransformation (such as discrete cosine transformation), and thequantization module 42B quantizes the frequency domain data matrix C toa quantized frequency domain data matrix Q. The quantization correctionmodule 42C can achieve AC/DC predictions to properly correct the outcomeof the quantization module 42B. All in all, the frequency-domaintransformation/quantization module 40 performs the frequency-domaintransformation/quantization for the block B of the picture to generatethe quantized frequency domain data matrix Q. Furthermore, the innermemory 52 supports operations of each above-mentioned module by storingdata for the operations.

In order to control access of the quantized frequency domain data matrixQ to the inner memory 52, the register module 50 of the presentinvention registers a bit plane N as a reference matrix. The bit plane Nis a two-dimensional reference matrix, which includes a plurality ofone-bit reference elements Nij each corresponding to a data element Qijof the data matrix Q, and it uses digital “0” and “1” to representwhether values of the data element Qij are zero (null) or not. Becauseeach reference element Nij is only a one-bit data, the register module50 can be simply achieved by a shift register; the shift keying controlmodule 54 can control bit shifts of the register module 50 to accesseach value of the bit Nij. The decision module 48A and the checkingmodule 48B can control the data matrix Q in accessing the inner memory52 based on each bit Nij of the bit plane N.

Please further refer to FIG. 5 (and FIG. 4) to see the registerconfiguration of the bit plane N in the register module 50. FIG. 5illustrates an implementation diagram of the bit plane N configurationin the present invention. In present image compression standards (suchas MPEG), a block B contains 8*8 pixels. In this situation, thequantized frequency domain data matrix Q also contains 8*8 dataelements, so that the bit plane N should have 8*8 bits correspondingly.In the present invention, the register module 50 can achieve eight 8-bitshift registers with a 1-bit shifter. As illustrated in FIG. 5, thequantized frequency domain data matrix Q includes 8*8 data elementsQ00-Q07, Q10-Q17 . . . Q70-Q77. Contrarily, the bit plane N alsoincludes 8*8 bits N00-N07, N10-N17 . . . N70-N77; the bit N00-N07 formsa row R0, the bit N10-N17 forms a row R1, and so on.

As to implementing processes of image data compression in the presentinvention, it can be discussed in two aspects. First of all, after thefrequency-domain transformation/quantization module 40 generates thedata matrix Q, the data matrix Q is stored (written) into the innermemory 52. In this process, the present invention can construct acorresponding bit plane N based on each data element Qij; meanwhile, thedecision module 48A can determine that its corresponding data elementQij should be written into the inner memory 52 according to the value ofeach bit Nij. Please refer to FIG. 6 (also FIG. 4 and FIG. 5), whichillustrates the control of the decision module 48A on writing the dataelement when the present invention stores the quantized frequency domaindata matrix Q into the inner memory 52. As mentioned above, the datamatrix Q is a sparse matrix and its data elements are almost all null.For example, after the frequency-domain transformation/quantizationmodule 40 finishes its operations, it generates the quantized frequencydomain data matrix Q as shown in FIG. 6, the data elements Q00, Q01,Q11, Q21, and Q40 are non-null while the others are all null. As step62A is illustrated in FIG. 6, before the data matrix Q is stored intothe inner memory 52, its corresponding bit plane N is not yetconstructed, and each bit of the corresponding bit plane N is reset asdigit “0”. In the implementation of FIG. 6, it is assumed that each bitNij of the bit plane N represents nulls of its corresponding dataelement Qij by digit “0”, and non-nulls by digit “1”.

After the frequency-domain transformation/quantization where module 40finishes quantizing the first data element Q00 of the data matrix Q, abit in its corresponding bit plane should be digit “1” for its non-nullquantized value, and in step 62B shown in FIG. 6, the digit “1”registers into the most right bit of the row R0 by one bit shift. At thesame time, the decision module 48A follows the non-null value of thedata element Q00 by the digit “1”, so that the data element Q00 iswritten into the inner memory 52. In step 62C, after thefrequency-domain transformation/quantization module 40 continuesquantizing subsequent data elements and generating the data element Q01,another digit “1” is needed in the bit plane N for the quantized valueis also non-null, and this digit “1” is stored into the rightmost bit ofthe row R0 by bit shift. Therefore, the former digit “1” correspondingto the data element Q00 shifts one bit to the left side (along with thearrow 64). Meanwhile, the decision module 48A makes the non-null dataelement Q01 written into the inner memory 52 a digit “1” correspondingto the data element Q01.

In step 62D, the frequency-domain transformation/quantization module 40generates the third quantized data element Q02, a digit “0” is storedinto the rightmost bit of the row R0 by a one bit shift for its nullquantized value. The two digit “1”s corresponding to the data elementsQ00, Q01 continue shifting one bit to the left side. The decision module48A does not write the data element Q02 into the inner memory 52 basedon the digit “0” corresponding to the data element Q02 to reduce accesstime to the inner memory 52.

According to similar steps, when the frequency-domaintransformation/quantization module 40 outputs quantized data elementsQ03 to Q07 in turn, each bit in the bit plane N corresponding to thedata element is stored into the row R0 by bit shifts, and the decisionmodule 48A can determine whether the data element be written into theinner memory 52 based on each bit corresponding to the data element. Instep 62E, the frequency-domain transformation/quantization module 40generates the quantized data element Q07, and its corresponding digit“0” is also stored in the row R0 by one bit shift; the decision module48A therefore does not make the data element Q07 written into the innermemory 52. To this point, the frequency-domaintransformation/quantization module 40 has already outputted all dataelements Q00 to Q07 of the first row of the data matrix Q, so that a rowR0 of the bit plane N has been established. Following that, thefrequency-domain transformation/quantization module 40 continuesoutputting the data elements Q10 to Q17 of the second row of the datamatrix Q, and a row R1 of the bit plane N records bits eachcorresponding to the data element by bit shifts, so that the decisionmodule 48A controls the inner memory 52 to access these data elements.By this method, after the frequency-domain transformation/quantizationmodule 40 outputs all data elements of the quantized frequency domaindata matrix Q, the bit plane N is established. Please refer to FIG. 7(also FIG. 4 and FIG. 6). Following the implementation in FIG. 6, FIG. 7illustrates a schematic diagram after the establishment of the bit planeN; each bit Nij corresponds to one data element Qij of the data matrixQ.

In the implementation of the present invention in FIG. 6 and FIG. 7,owing to only five non-nulls in the data matrix Q, the inner memory 52should be accessed for five times when the whole data matrix Q is storedinto the inner memory 52. In comparison, the prior art processingcircuit, which does not undergo the null/non-null decision when storingthe data matrix Q, so that even if the data element Qij is null, itshould be written into the inner memory, which occupies a lot of memoryresources. Moreover, even if the data element Qij is null, it does notrepresent that this data element Qij is only one digit “0” data for thedata element Qij should record its value by a few bits, and it alsorepresents that the present technique needs a lot of memory resources toaccess null data element Qij.

In some cases (for example, when going to alternating/direct currentprediction), the quantization correction module 42C corrects some dataelement Qij (such as changing non-nulls to nulls in reasonablesituations), or corrects bits corresponding to the bit plane N based onthe corrected outcome of the quantization correction module 42C at thesame time. Please refer to FIG. 8. FIG. 8 illustrates a schematicdiagram showing the present invention register module 50 correcting thebit plane N. This correction usually involves the data elements Q00 toQ07 and Q00 to Q70, so that it can correct each bit corresponding toeach data element at the same time by bit shifts based on theillustration in FIG. 8.

After non-null data elements of the data matrix Q are stored into theinner memory 52 and a corresponding bit plane N is established, thepresent invention can control access to the data matrix Q based oninformation of the bit plane N as the data matrix Q is read out. Asdiscussed in FIG. 2 and related statements, the quantized frequencydomain data matrix Q is read out from the inner memory to undergo aserial scanning, and each data element of the two-dimensional datamatrix Q is arranged into an one-dimensional data matrix based on aspecified order. Please refer to FIG. 9 to FIG. 11 (and FIG. 5). Intypical image data de-/compression standards, there are three commonlyused serial scanning sequences, which are alternate vertical scanning,alternate horizontal scanning, and zig-zag scanning; the scanningsequences of these three type are shown in FIG. 9 to FIG. 11. From FIG.9 to FIG. 11, each data element Qij of the data matrix Q note is markedwith a symbol to represent scanning sequence of the data element; thesmaller the symbol, the earlier scanning time. For example, in FIG. 9,each data element Qij is arranged in an one-dimensional matrix by anorder: Q00, Q10, Q20, Q30, Q01, Q11, Q02, Q12, Q21, Q31, Q40, Q50, Q60,Q70, Q71, Q61, and etc. to Q47, Q57, Q67, Q77. In FIG. 10, each dataelement Qij is arranged in a one-dimensional matrix by an order: Q00,Q01, Q02, Q03, Q10, and etc. to Q74, Q75, Q76, Q77.

In general, within the quantized frequency domain data matrix Q, thedata element Q00 represents a direct current quantity of itscorresponding block B in frequency domain (therefore, it is also namedas direct-current frequency-domain element); contrarily, other dataelements are alternating current quantities in frequency domain (alsonamed alternating-current frequency-domain element). In the data matrixQ, data elements far away from the data element Q00 (such as dataelements in the lower-right corner of the matrix Q) may be nulls astheir corresponding frequency goes higher. Therefore, when arrangingeach data element of the data matrix Q in a one-dimensional matrix, thescanning sequences of FIG. 9 to FIG. 11 start near the upper-left cornerdata element (data elements near the data element Q00) to facilitate thefollowing running length coding.

In the present invention, when reading each data element of the datamatrix Q stored in the inner memory 52 by the scanning sequence, eachbit corresponding to the bit plane N can also be accessed by thescanning sequence to determine whether it needs to read correspondingdata elements from the inner memory 52 based on bit values. Furthermore,the present invention can check nulls of other data elements (not yetread) when reading frequency domain data elements; if the other dataelements are all nulls, the data elements are prevented from being readdirectly and quickly to reduce the inner memory 52 access time. Torealize the above checking step, the checking module 48B of the presentinvention (shown in FIG. 4) processes an “OR” operation to every bit ofthe bit plane N to gain a flag STP (that is: STP=!(R0 IR1 IR2 IR3 IR4IR5 IR6 IR7)), and determines if the scanning step finishes according tothe flag STP.

Please refer to FIG. 12 and FIG. 13 (also FIG. 4, FIG. 7, and FIG. 9)illustrating the situation when the present invention processes theserial scanning. Continuing with the implementation in FIG. 7, if thedata matrix Q and its corresponding bit plane N are as shown in FIG. 7,the data matrix Q undergoes the serial scanning by the order of FIG. 9.As step 66A in FIG. 12 shows, before the serial scanning starts, the bitplane N is as illustrated in FIG. 7. After the serial scanning starts,owing to the digit “0” of the flag STP (there are digit “1”s in the bitplane N), the checking module 48B decides to scan. According to thescanning sequence (as FIG. 9 illustrates), the checking module 48Bshould gain a value of the data element Q00 first, and then the decisionmodule 48A determines if it should read the data element Q00 from theinner memory 52 based on the first bit of the row R0 (the leftmost sidebit). Because the first bit of the row R0 is digit “1” the data elementQ00 is non-null, so that the decision module 48A decides that the dataelement Q00 should be read from the inner memory 52. After reading thedata element Q00, the shift keying control module 54 (in FIG. 4) shiftseach bit of the row R0 one bit to left side, and the most right bitstores a digit “0” (it is also the “X” bit in FIG. 12) as shown in step66B. The bit shifting represents that the bit corresponding the dataelement Q00 in the row R0 has been properly handled.

In step 66B, the checking module 48B does not stop serial scanning asthe flag STP is still digit “0” (wherein bit noted as “X” is digit “0”).According to the scanning sequence shown in FIG. 9, it should gain thevalue of the data element Q10, so that the decision module 48Adetermines whether the data element Q10 should be read based on theleftmost side bit of the row R1 (the bit corresponding to the dataelement Q10). Because the bit is digit “0”, the decision module 48Adecides not to read the data element Q10 from the inner memory 52 (infact, the inner memory 52 need not store the null data element Q10), andcan cooperate with the data address generator 46 to deal with the dataelement Q10 to reduce access to the inner memory 52. After the decisionto read the data element Q10, the row R1 in the bit plane N shifts onebit to the left and stores a digit “0” in the rightmost side (noted as“X”) to represent that the bit corresponding the data element Q10 in therow R1 has been properly handled. The bit plane N after bit shifts is asshown in step 66C.

In step 66C, the checking module 48B continues serial scanning for theflag STP is still digit “0” (wherein two bits noted as “X” are digit“0”s). According to the scanning sequence shown in FIG. 9, reading ofthe data element Q20 is performed, and the decision module 48A decidesnot to read the data element Q20 as the first bit of the row R2 is digit“0”. After the decision to read the data element Q20, the row R2 of thebit plane N shifts one bit to left side and stores a digit “0” in therightmost side (noted as “X”), which becomes the illustration in step66D.

Similarly, in step 66D, the flag STP is still digit “0”, so that thedata element Q30 undergoes the serial scanning, and the decision module48A decides not to read the data element Q30 as the first bit of the rowR3 is digit “0”. After the decision to read the data element Q30, therow R3 shifts one bit to left side and stores a digit “0” (noted as“X”), which becomes the illustration in step 66E.

In step 66E, the flag STP is digit “0”, so that the data element Q01undergoes the serial scanning (as FIG. 9 illustrates). Because the firstbit of the row R0 (after the bit shifts in step 66A, the bit correspondsto the data element Q01) is digit “1”, the decision module 48A decidesthe data element Q01 should be read from the inner memory 52. After itcompletes dealing with the data element Q01, the row R0 shifts one bitto the left and stores a digit “0” (noted as “X”), as related by theillustration in step 66F.

As the serial scanning continues, processed data elements increase, andthere should be more and more digit “0”s in the bit plane N since bitscorresponding to processed data elements are noted as digit “0” (or the“X”). As shown in step 66F to 66J (from FIG. 12 to FIG. 13), after eachdata element undergoes the serial scanning, rows with corresponding bitsin the bit plane N record a digit “0” (or the “X”) by bit shifts, sothat the checking module 48B can decide whether the serial scanningshould continue based on the bit plane N after bit shifts.

As FIG. 13 illustrates, in step 66K, the serial scanning goes to thedata element Q40, and the decision module 48A decides the data elementQ40 should be read from the inner memory 52 based on the first bit ofthe row R4; the row R4 of the bit plane N record a digit “0” (wherenoted the “X”) by bit shifts to left side, which becomes theillustration in step 66L. In step 66L, owing to all bits in the bitplane N being digit “0”s, there is no unprocessed data elements, and theflag STP changes to digit “1”, so that the checking module 48B finishesthe serial scanning based on the flag STP.

In other words, when the serial scanning goes to each data element oneby one, there are two mechanisms in the present invention to reduceaccess to the inner memory. One is operation of the decision module 48A,which only accesses non-null data elements. The other mechanism isoperation of the checking module 48B, which determines nulls ofun-processed data elements based on the flag STP. If all of them arenulls, it can finish the serial scanning directly and quickly withoutaccessing the left null data elements to the inner memory 52. By the bitplane N registered in the register module 50, the present invention candetermine a null of each data element quickly without accessing theinner memory. In comparison with the prior art technique shown in FIG.3, owing to lack of the above mechanisms to determine null of each dataelement, when processing the serial scanning, the prior art must readall data elements in the data matrix, no matter how many are nulls.Therefore, the prior art technique wastes a lot of memory resources.

As implementations of FIG. 12 and FIG. 13 illustrate, after processingeach data element, the present invention shifts one bit to the left sideof the same row to refresh the bit plane, and shifts the second bit inthe same row to the leftmost side (also the first bit of the row), sothat the decision module 48A can decide null by the leftmost bit of thecorresponding row when the second data element of the same row undergoesthe access decision. As step 66A, 66E, and step 66G illustrate in FIG.12 and FIG. 13, in step 66A, the bit corresponding to the data elementQ01 shifts to the leftmost side of the row R0, so that the decisionmodule 48A can decide null of the data element Q01 (in the same row ofthe data element Q00) based on the left-most side bit of the row R0 instep 66E. In step 66E, the bit corresponding to the data element Q02shifts to the leftmost side of the row R0 again. In step 66G, thedecision module 48A decides null of the data element Q02 (in the samerow of the data element Q00 and Q01) based on the most left side bit ofthe row R0. Observing the scanning sequences in FIG. 9 and FIG. 11, thescanning order of each data element is prior to its right side dataelement for the same row data elements, so that the bit shifts towardleft side in FIG. 12 and FIG. 13 can fit the scanning sequences in FIG.9 and FIG. 11.

Contrarily, in order to process the serial scanning by the scanningsequence shown in FIG. 10, the scanning order of each data element isuncertain prior to its right side data elements. As FIG. 10 illustrates,in the second row, the scanning orders of the data element Q14, Q15,Q16, and Q17 from left to right are 17, 16, 15, and 14. Similarly, inthe third row, the scanning orders of the data element Q22 and Q23 are19 and 18. In order to fit the bit shift method of the bit plane N tothe scanning sequence in FIG. 10, the register module 50 of the presentinvention can be constructed as the circuit in FIG. 14. As FIG. 14illustrates, aimed at the row R1 and R2 of the bit plane N, the presentinvention includes a related multiplexer 68 and a shift keyingcontroller 70 for controlling bit shift directions to achieve differentshift control, so that the register module of the present invention canchange to support all scanning sequences in FIG. 9 to FIG. 11. The shiftkeying control module 54 of the present invention can change the bitshift method by a one-bit control signal Cb.

Please refer to FIG. 15, FIG. 16 (and FIG. 14). FIG. 15 and FIG. 16illustrate that the register module 50 processes bit controls indifferent situations in FIG. 14. As FIG. 15 illustrates, when thecontrol signal Cb is digit “1”, the bit shift direction is toward left(omitted unable bit shift directions), so that the present invention cancontrol memory access in the serial scanning by the scanning sequencesin FIG. 9 and FIG. 11. On the other hand, when the control signal Cb isdigit “0”1, its enabled bit directions are shown in FIG. 16 to supportrefreshing of the bit plane N when the serial scanning goes by thescanning sequence shown in FIG. 16. Corresponding to the scanningsequences of the data element Q14 to Q17 in the second row, the bits N14to N17 undergo bit shifts by shifting toward the right side; in otherwords, the bit N17 first shifts to the most left side of the row R1, andthen the bit N16, N15, and N14 go after. Similarly, the bits N22 and N23of the row R2 fit the data element Q22 and Q23 by shifting toward theright side. That is to say, when processing the serial scanning based onthe sequence in FIG. 10, the present invention can shift bits in asimple way to access bits corresponding to each data element, andcontrol access of the data element in the inner memory 52 accordingly.

Please refer to FIG. 17. FIG. 17 illustrates another implementationfunction diagram of the present invention, a processing circuit 80. Theprocessing circuit 80 can decompress compressed image data, and includesa central processing unit 82, a memory access module 86, an inner memory102, a dynamic compensation module 88, an inverse scanning module 92A, adata address generator 92B, a variable length decoding module 92C, and atransformation module 90. To match operations of the present invention,the processing circuit 80 further includes a register module 100, ashift keying control module 104, and a decision module 98. The centralprocessing unit 82 controls operations of the processing circuit 80, andthe memory access module 86 accesses an outer memory 84. Besides, thevariable length decoding module 92C, the data address generator 92B, andthe inverse scanning module 92A can decode one-dimensional data matrix R(please refer to FIG. 2) to two-dimensional quantized frequency domaindata matrix Q. After de-quantizing the data matrix Q, the transformationmodule 90 can process an inverse frequency-domain transformation (suchas inverse discrete cosine transformation) to generate correspondingpixels of a block matrix, and the dynamic compensation module 88 canprocess a dynamic compensation to decompress image data. The innermemory 102 supports memory resources of the above module operations.

As the variable length decoding module 92C, the data address generator92B, and the inverse scanning module 92A operate, the one-dimensionaldata matrix R after running length coding and Huffman coding is decodedto a one-dimensional data matrix S (in FIG. 2) to generate each dataelement Qij. After the inverse scanning, data elements of theone-dimensional data matrix S are rearranged to a two-dimensional datamatrix Q, and the data matrix Q is stored into the inner memory 102 forfollowing de-quantization/inverse frequency-domain transformation. Whenthe data matrix Q is stored into the inner memory 102, the presentinvention can generate a corresponding bit plane N in the registermodule 100, and the decision module 98 can determine nulls of the dataelement Qij based on each bit of the bit plane N, and determine whetherit should be written into the inner memory 102. As the variable lengthdecoding module 92C, the data address generator 92B, and the inversescanning module 92A finish decoding the data element Qij, it can be surewhether is there any null in the data element Qij. Furthermore, the bitNij of its corresponding bit plane N can be confirmed, and stored intothe register module 100 by bit shifts. Meanwhile, the decision module 98can decide whether the data element Qij be should written into the innermemory 102 based on the bit Nij. If the data element Qij is null, it isprevented from being written into the inner memory 102, achieving onegoal of the present invention to reduce access to the inner memory 102.

After the data matrix Q is stored in the inner memory 102, itscorresponding bit plane N is complete. When reading the data matrix Qand processing de-quantization, the decision module 98 of the presentinvention can decide that whether its corresponding data element Qijshould be read from the inner memory 102 based on each bit Nij of thebit plane N. If a bit Nij corresponding to some data element Qijrepresents that the data element is null, the decision module 98 doesnot read the data element Qij (actually, the data element is not storedin the inner memory 102), and it can cooperate with the data addressgenerator 92B and its generated address information to finish dealingwith the data element Qij. Therefore, the present invention can reduceaccess time of the inner memory 102 by controlling access to non-nulldata element Qij.

When processing the above de-quantization, the present invention cankeep bit plane information by a rotational bit shift method. Pleaserefer to FIG. 18. FIG. 18 illustrates a register module 100implementation diagram of the rotational bit shift method. For example,when reading the data element Q00 to Q07 of the first row, the decisionmodule 98 can determine practical reading of the data element Q00 by theleftmost bit of the row R0. After that, each bit of the row R0 shifts abit to the left to make the bit corresponding to the data element Q01 toshift to the leftmost side of the row R0, and the bit corresponding tothe data element Q00 shifts to the rightmost side of the row R0 by therotational method. Following that, when processing reading of the dataelement Q01, the decision module 98 still can determine the reading ofthe data element Q01 based on the leftmost bit of the row R0 (since itscorresponding bit has been shifted to the most left side of the row R0).After processing the data element Q01, each bit of the row R0 shiftstoward the left similarly, and the bit corresponding to the data elementQ01 again shifts to the rightmost side of the row R0 by the rotationalmethod. Therefore, after processing readings of the data elements Q00 toQ07, the row R0 of the bit plane N just rotates to the initial condition(the original condition when the bit plane N is just set up) to keepinformation of the row R0. In this way, after processing each reading ofthe data element Qij, the bit plane N still keeps all correspondinginformation.

By the information provided by the bit plane N, the present inventioncan further simplify the inverse transformation when processing inversefrequency-domain transformation. Those skilled in the art will recognizethat processing two-dimensional inverse frequency-domain transformationis equivalent to processing one-dimensional inverse frequency-domaintransformation twice. When the one-dimensional inverse frequency-domaintransformation progresses, if there are only direct current frequencydomain data elements that are non-nulls in some row, and otheralternating current frequency domain data elements are all nulls, theone-dimensional output matrix provided by the one-dimensional inversefrequency-domain transformation is a constant matrix (that is, eachelement is a constant). In the present invention, because the bit planeN has already recorded null conditions of each frequency domain dataelement, it can use the information provided by the bit plane N to makesure that if each row of the frequency domain data matrix has theabove-mentioned characters.

As FIG. 17 illustrates, in the processing circuit 80 of the presentinvention, two-dimensional inverse frequency-domain transformation isperformed by the transformation module 90, and the transformation module90 includes a transformation-checking module 94, a constant operationmodule 96A, and a transformation operation module 96B for theone-dimensional inverse frequency-domain transformation. When some rowof the frequency domain data matrix undergoes the one-dimensionalinverse frequency-domain transformation, the transformation-checkingmodule 94 can check if there are only direct current frequency domaindata elements that are non-nulls in the row by its corresponding row inthe bit plane N, or if there is only the leftmost bit in thecorresponding row of the bit plane N that is null. In the abovesituation, the row of the frequency domain data matrix has only directcurrent frequency domain quantities, and other alternating currentfrequency domain quantities are nulls. The one-dimensional output matrixprovided by the one-dimensional inverse frequency-domain transformationshould be a constant matrix. At this time, the constant matrix can begenerated by the constant operation module 96A as an output matrix Op ofone-dimensional inverse frequency-domain transformation. Relatively, ifthe corresponding row of the bit plane N has non-null alternatingcurrent frequency domain data elements, the transformation operationmodule 96B processes the one-dimensional inverse frequency-domaintransformation to generate corresponding output matrix Op.

Please refer to FIG. 19 (and FIG. 17). FIG. 19 illustrates the processof the above-mentioned one-dimensional inverse frequency-domaintransformation by an algorithm. If frequency domain data element Bm0,Bm1 . . . Bm7 (m is a constant) of some row undergo the one-dimensionalinverse frequency-domain transformation, bit Nm0, Nm1 . . . . Nm7 of thebit plane corresponding to the above frequency domain data elementsrepresent null conditions of the frequency domain data elements. Duringthe one-dimensional inverse frequency-domain transformation, the presentinvention can check if all the alternating current frequency domain dataelements are nulls by these corresponding alternating current frequencydomain data elements, the bit Nm1, Nm2 . . . Nm7. If true, elements Op0,Op1 to Op7 of the output matrix Op are set as a constant C0 (thisconstant can be generated by the constant operation module 96A). Iffalse, the transformation operation module 96B processes aone-dimensional inverse frequency-domain transformation to generate theoutput matrix Op. The output matrix of the constant operation module 96Aor the transformation operation module 96B undergoes anotherone-dimensional inverse frequency-domain transformation, and then thecorresponding block of the frequency domain data matrix is gained.

To sum up, in the process of image data de-/compression (or de-/coding),the inner memory of the processing circuit is necessary to processaccess of a frequency domain data matrix. This frequency domain datamatrix is usually a sparse matrix with many null data elements. However,in prior art techniques, this character is not used, so that each dataelement of the frequency domain data matrix should access the innermemory, which costs a lot of memory resources and increases the innermemory bandwidth demand.

In comparison to the prior art, the present invention registers a bitplane by a register module formed by a simple shift keying register, andeach bit of the bit plane records null conditions of each frequencydomain data element correspondingly. Therefore, it can access each bitof the bit plane by the bit shift method fast and conveniently, check ifeach frequency domain data element is null based on the bit planeinformation, control inner memory access of the frequency domain data,and make the process of image data de-/compression more speedy. In theimplementation mentioned from FIG. 4 to FIG. 16, the present inventionprevents access of the null frequency domain data elements fromoccupying the inner memory resources based on the bit plane information,and makes the serial scanning process faster. Similarly, in theimplementations of FIG. 17 and FIG. 18, the bit plane information makesthe null frequency domain data element not to be written into the innermemory, and makes the inverse frequency-domain transformation faster.According to the sparse character of the frequency domain data matrix,the present invention releases a lot of memory resources in the processof image data de-/compression, and reduces the inner memory bandwidthdemand and related power dissipation, so that costs of designing andproducing related processing circuits can be curtailed, and efficienciespromoted. In each implementation of the present invention, each modulecan be achieved by hardware circuits, or achieved by processing firmwareprograms in the central processing unit of the processing circuit. Theabove-mentioned processing circuits 30 and 80 can be combined as asingle processing circuit including de/compression functions. Forexample, the decision modules of the processing circuit 30 and 80 can becombined to a decision module, which controls access of non-null dataelements in the inner memory when de/compressing. Similarly, it can alsoregister the bit plane by one register module in the de/compressionprocess.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device may be made while retainingthe teachings of the invention. Accordingly, the above disclosure shouldbe construed as limited only by the metes and bounds of the appendedclaims.

1. A data coding/decoding method comprising: reading a frequency-domainmatrix, the frequency-domain matrix comprising a plurality offrequency-domain elements; providing a reference matrix comprising aplurality of reference elements each corresponding to a frequency-domainelement, each reference element representing whether its correspondingfrequency-domain element fits a default or not; and taking atransformation step for generating an output matrix based on thefrequency-domain matrix, the transformation step comprising: taking atransformation checking step for checking if the reference matrix fits adefault matrix; if the reference matrix does not fit the default matrix,a corresponding output matrix is generated by proceeding to atransformation operation for the frequency-domain matrix; and if thereference matrix fits the default matrix, the frequency-domain matrix isprevented from undergoing the transformation operation and the outputmatrix is a constant matrix.
 2. The data coding/decoding method of claim1 wherein at least one frequency-domain element is a direct currentfrequency-domain element and other frequency elements are alternatingcurrent frequency-domain elements among the plurality offrequency-domain elements; wherein when the reference matrix fits thedefault matrix, each reference element corresponding to each alternatingcurrent frequency-domain element in the reference matrix represents thatthe alternating current frequency-domain element fits the default. 3.The data coding/decoding method of claim 2 further comprising: when thereference matrix fits the default matrix, a constant operation step isperformed for generating the constant matrix by working out a constantvalue based on the direct current frequency-domain element so that aplurality of elements of the constant matrix equal the constant value.4. The data coding/decoding method of claim 1 wherein the default isnull.
 5. The data coding/decoding method of claim 1 wherein thetransformation operation is an inverse discrete cosine transformation.6. A processing circuit for data coding/decoding comprising: a memorycapable of storing a frequency-domain matrix, the frequency-domainmatrix comprising a plurality of data elements; a register module forstoring a reference matrix wherein the reference matrix comprises aplurality of reference elements each corresponding to a frequency-domainelement, each reference element for representing whether itscorresponding frequency-domain element fits a default or not; and atransformation module for providing a corresponding output matrix basedon the frequency-domain matrix, the transformation module comprising: atransformation operation module; and a transformation checking modulefor checking if the reference matrix fits a default matrix; wherein ifthe reference matrix does not fit the default matrix, the transformationchecking module triggers the transformation operation module to proceedto a transformation operation for generating a corresponding outputmatrix, and if the reference matrix fits the default matrix, thetransformation checking module is prevented from triggering thetransformation operation module to proceed to the transformationoperation for generating a corresponding output matrix and the outputmatrix is a constant matrix.
 7. A processing circuit for datacoding/decoding of claim 6 wherein at least one frequency-domain elementis a direct current frequency-domain element and other frequencyelements are alternating current frequency-domain elements among theplurality of frequency-domain elements; wherein when the referencematrix fits the default matrix, each reference element corresponding toeach alternating current frequency-domain element in the referencematrix represents that the alternating current frequency-domain elementfits the default.
 8. The processing circuit for data coding/decoding ofclaim 7 further comprising: a constant operation module; wherein whenthe reference matrix fits the default matrix, the transformationchecking module triggers the constant operation module to generate aconstant value and the constant matrix based on the direct currentfrequency-domain element so that a plurality of elements of the constantmatrix equal the constant value.
 9. The processing circuit for datacoding/decoding of claim 6 wherein the default is null.
 10. Theprocessing circuit for data coding/decoding of claim 6 wherein thetransformation operation module is capable of performing an inversediscrete cosine transformation.